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IP Quality Means Something Different if You Are Making Changes

How to evaluate the quality of semiconductor intellectual property (IP)? That sounds like a question that was settled years ago, at least for industry-standard interface IP. But increasingly today, system designers—especially those who develop their own ASICs or FPGA-based implementations—use supposedly standard IP in distinctly non-standard ways. We overclock physical-layer IP. We bypass protocol layers […]

CATEGORIES : All, Design Challenges, System Architecture/AUTHOR : Ron Wilson

Memory Bandwidth Takes Center Stage at Hot Chips Conference

The pursuit of memory bandwidth has become a dominant theme in system design. SoC designers, whether they use ASIC or FPGA technologies, must plan, architect, and implement with memory at the center of their thinking. System designers must, with a clear understanding of memory traffic patterns, provision the ports the chip designers created. Even memory […]

CATEGORIES : All, Design Challenges, System Architecture/AUTHOR : Ron Wilson

The Third Decade: The FPGA as SoC

In 2003, amidst the recessionary hangover from the dot-com crash, Altera began its third decade. It was a year of endings: the tragic loss of the space shuttle Columbia, the last contact with the spacecraft Pioneer 10, the last VW Beetle from the assembly line. And it was a year of beginnings: the Iraq War, […]

CATEGORIES : All, Design Challenges, System Architecture/AUTHOR : Ron Wilson

FinFETs, Analog Circuits, and Your Next System Design

Everyone is talking about FinFETs—arguably the biggest change in transistors since commercialization of the MOSFET in the 1960s. And nearly everyone—except perhaps enthusiasts of fully-depleted silicon on insulator (FDSOI)—accepts that beyond the 20 nm node, FinFETs are the future of SoCs. But what does that future hold for a system developer who will use these […]

CATEGORIES : All, Design Challenges, System Architecture/AUTHOR : Ron Wilson

Powering SoCs: Where Do the Regulators Go?

Increasingly sophisticated SoCs, integrating many system components onto a single die, have in general simplified the system designer’s job. But these chips have made the power-delivery subsystem more complex. What used to be a straightforward task of routing Vcc from a supply connector to the ICs has become the design of an active network as […]

CATEGORIES : All, Design Challenges, System Architecture/AUTHOR : Ron Wilson